Cisco ASIC Design Technical Leader – & Timing Constraints Focus 

United States, California, San Jose 

29088181

The application window is expected to close on: 1/17/24

This position will be onsite in San Jose 5 days per week

Your Impact

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll contribute to developing next-generation networking chips.

Responsibilities include:

• Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
• Option to also do block level RTL design or block or top-level IP integration.
• Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
• Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
• Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
• Creating fullchip clocking diagrams and related documentation.

Minimum Qualifications:

• Bachelor’s Degree in Electrical or Computer Engineering with 8+ years of ASIC or related experience or Master’s Degree in Electrical or Computer Engineering with 6+ years of ASIC or related experience
• Experience with block/full chip SDC development in functional and test modes.
• Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus
• Understanding of related digital design concepts (eg. clocking and async boundaries)
• Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System Verilog programming

Preferred Qualifications:

• Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence)
• Experience with Spyglass CDC and glitch analysis
• Experience using Formal Verification: Synopsys Formality and Cadence LEC.
• Experience with scripting languages such as Python, Perl, or TCL