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Intel SoC Physical Design Engineer United States, Oregon, Hillsboro 288362796
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Your responsibilities may include but not be limited to:
Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools.
Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF.
Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking.
Analyzes results and makes recommendations to fix violations for current and future product architecture.
Participating in the development and improvement of physical design methodologies and flow automation.
Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs.
The ideal candidate should exhibit behavioral traits that indicate:
Self-motivator with strong problem-solving skills.
Excellent interpersonal skills, including written, verbal, and presentation communications.
Attention to detail and organizational skills.
Ability to work as part of a team and collaborate in a high-paced atmosphere.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Bachelor's degree in electrical engineering, Computer Engineering or related field with 5+ years of relevant experience OR
Master's degree Electrical Engineering, Computer Engineering or related field with 3+ years of relevant experience
The relevant experience would include one of the following areas:
Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.
Static timing analysis constraint understanding and generation, clock stamping, and timing closure.
Multiple Power Domain analysis using standard Power Formats UPF or CPF.
Preferred Qualifications:
6+ years of experience in physical design using industry EDA tools.
7+ years of experience in backend design and/or integration
Product development and delivery on leading edge process nodes
Experience in Python/Perl/TCL programming languages
Position of Trust
offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
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