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Apple Design Verification Engineer Sweden 285388018
28.03.2024
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Key Qualifications
- Deep knowledge of System Verilog test-bench language and UVM
- Validated experience developing scalable and portable test-benches
- Validated experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations
- Experience with IP verification methodology
- In lieu of UVM knowledge, C/C++ authority knowledge
- Significant experience with DDR PHY or Controller
- Deep knowledge of one of the scripting languages: Python, Perl, TCL
- Deep knowledge of formal verification methodology
Description
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to the following:Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring scalable and portable environment. Develop verification plans for all features under your care. Implement verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. Develop block, IP and SoC level test-benches.
Education & Experience
BS degree in technical discipline with minimum 3 years of relevant experience.
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