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What You Can Expect
Architect and implement simulation test bench in UVM.
Develop and execute test-plans for verifying correctness and performance of the design.
Own and debug failures in simulation to root-cause problems
Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations
Coach and mentor junior engineers of the team when necessary to achieve successful project outcomes.
What We're Looking For
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. OR Master’s degree in Computer Science, Electrical Engineering or related fields with 10-12 years of experience. OR PhD in Computer Science, Electrical Engineering or related fields with 8-10 years of experience.
Strong background in SoC verification and test bench development using UVM, System Verilog, C/C++, and DPI.
Strong verification skills, understanding of methodology (object oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations, data structure).
Must have effective interpersonal and teamwork skills.
Participate in problem solving and quality improvement activities.
Demonstrate initiative and a bias for thoughtful action.
Grounded, detail-oriented, always backs up ideas with facts.
Must have the ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.
Expected Base Pay Range (USD)
168,920 - 253,000, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
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