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Google ASIC Design Verification Engineer Machine Learning Early Career United States, Wisconsin, Madison 283222813
29.01.2025
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
- 1 year of experience coding in SystemVerilog through internships or work experience.
- Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog for FPGAs, ASICs, or SOCs.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field.
- Experience with verification methodology such as UVM/OVM/VMM.
- Experience with the full verification life cycle.
- Experience in SystemVerilog.
- Excellent team player, problem-solving, and communication skills .
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