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Google Senior RTL Design Engineer Silicon United States, California, Mountain View 279450379
24.07.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- 6 years of experience with IP Development or Integration.
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
- Experience with a scripting language like Perl or Python.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
- Experience with FPGA and emulation platforms.
- Experience with high performance and energy efficient design techniques.
- Experience with ASIC Verification or DFT.
- Knowledge in Processor Cores, Buses/Fabric/NoC, Debug/Trace, Interrupts, or Clocks/Reset.
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