Marvell Wafer Sort Technician Weekend Night 

United States, California 

269317997

What You Can Expect

The responsibilities include but not limited to.

• Design verification for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications.
• Use and improve UVM DV environment
• Improve the design methodology and flow.
• Collaborate with Analog/DSP/Digital Design/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines.
• Provide the support to the product teams, for both pre and post silicon

What We're Looking For

MSEE with 8+ years of experience.

Must be proficient in the following skills:

• Fundamental concepts in digital logic design
• Understand ASIC verification flows and methodologies
• Verilog,SystemVerilog, UVM
• UNIX Shell scripting (Csh, Bash)

Highly desirable skills:

• Experience with VIPs
• Formal verification
• Low power design
• MATLAB and C/C++ based system simulation and evaluation
• DSP function hardware implementation knowledge
• Strong Perl and Python scripting

Expected Base Pay Range (USD)

121,840 - 182,500, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at