Marvell Switch Architect United States, California 268096003
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What You Can Expect
You will completely own the
egress processor IP designIncluding:
Closely working with architecture team to understand the feature enhancement needs.
Implement a specification using RTL coding techniques.
Ensuring all quality criteria are met.
Must be familiar with Digital IC design methodologies, understand all stages of ASIC design flows, and experienced with state-of-the-art design tools.
Work with the physical design teams for synthesis and timing signoff.
Work with the Verification team on pre-silicon verification tasks such as reviewing the verification test plan, coverage analysis, and full-chip simulation and related debug.
Strong Knowledge of HDL and experience in Verilog coding, Perform RTL coding,
Strong Knowledge of logic synthesis and timing analysis.
Networking knowledge is a plus.
What We're Looking For
Master’s degree and/or PhD/Bachelor’s degree in Computer Science, Electrical Engineering or related fields with 4 to 20 years’ of relevant industry experience.
Experience with digital design microarchitecture development is a must.
Design/RTL experience in Verilog or SV is a must.
Experience with logic synthesis, synthesis constraint development and backend flow and static timing analysis.
Knowledge of scripting languages, such as PERL, Python
Ethernet protocols (IEEE 802.3, 802.1Q, 802.1D, Routing protocols) preferred.
L2 / L3 / L4 Ethernet protocol knowledge
Encryption / Authentication algorithms.
Precision Time Protocol (PTP, IEEE-1588)
Knowledge of GIT version control system
Good learning , problem solving interpersonal and communication skills.
Ability to be a part of a team, working in cooperation.
Self-motivated team player able to thrive in a fast-paced engineering environment.
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