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You will be part of SIFG (Server, IP & FW) team, working on designing & validating SoC & IPs for the state-of-the-art next Gen Server products.
Who You Are
Your responsibilities are as follows but not limited to:
Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools.
Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware.
Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability.
Enables acceleration of RTL development and improve emulation/FPGA model usability for pre-silicon verification, post-silicon validation, and software development.
Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing pre-silicon verification environments, test suites, and methodologies for emulation efficiency.
Develops and utilizes automation aids, flows, and scripts in support of emulation utilization.
Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model).
Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues.
Ability to work in a dynamic and team-oriented environment
Problem-solving skills, including debugging and brainstorming techniques
Strong written and verbal communication skills
You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must be pursuing a Master's Degree or PhD Degree in Computer Science, Computer Engineering, Electrical Engineering
Emulation concepts and debug experience; Exposure to System Verilog with OVM/UVM methodology
Preferred Qualifications
Scripting experience, Gate-Keeper usage, Triage failure parsing/assignments.
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