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Leads and manages silicon PCIe and CXL design teams that span across more than one area of functional development including logic design, verification, circuit design, and/or physical design for an IP and Subsystem.
Manages the engineering team resources, their functions, activities, responsibilities, and driving continuous improvement and silicon quality standards to ensure key factors such as power, performance, area, and cost are meeting requirements.
Provide leadership in PCIe and CXL protocol, including transaction layers, data link layers, and physical layers.
Drive innovation in design methodologies, techniques, and tools to improve performance, power efficiency, and latency.
Collaborate with cross-functional teams including hardware, software, and verification teams to ensure integrated and optimized PCIe designs for driving team results.
Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:
Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field. Master's Degree or Ph.D. may be preferred
Requires 8+ years of experience in design and development, with at least 3 years in a managerial or leadership role
Strong proficiency in RTL coding (Verilog/VHDL), FPGA/ASIC design flow, and EDA tools.
Expertise in PCIe architecture, protocols, and specifications preferred.
Strong leadership, team management, and organizational skills. Ability to inspire and motivate a technical team with excellent verbal and written communication skills.
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