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Apple RTL Design Engineer Australia, Victoria, Melbourne 263698824
06.06.2024
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Description
In this job you will be responsible for specifying and/or micro-architecting digital blocks in sophisticated mixed-signal circuits. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing significant assertions, debugging code, and otherwise interacting with the design verification team. You get to participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
Key Qualifications
- Deep knowledge of mixed signal concepts
- Deep knowledge of RTL design fundamentals
- Deep knowledge of Verilog and System-Verilog
- Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
- Solid understanding of synthesis, static timing, DFT is a huge plus
- Deep knowledge of System-Verilog assertions, checkers, and other design verification techniques
- Confirmed experience in scripting languages. Perl and Python
- Good understanding of Algorithm developments
- Strong communication and presentation skills
- SERDES knowledge is a plus
Education & Experience
BS degree in technical discipline with minimum 10 years of relevant experience.
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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