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Apple SoC Physical Design Engineer PnR United States, California, Sunnyvale 259804791
12.09.2024
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Description
Responsibilities would include: • Working with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. • Completing netlist to GDS2 implementation for partition(s) meeting schedule and design goals. • Timing, physical and electrical verification and driving the signoff closure for the partitions. • Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.
Minimum Qualifications
- Minimum BS.
- Basic understanding of logic gates.
Preferred Qualifications
- Previous internship/co-op, project work or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design.
- Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields.
- Experience with Verilog, VHDL, Python, Perl, TCL and/or SPICE.
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $58.61 and $88.29/hr, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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