Intel Graduate Intern Technical Standard cell library design layout 

India, Karnataka, Bengaluru 

251816787

Responsibilities may be quite diverse of a t technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school.A BS/BE/BTech in Electronics Engineering with exposure to designing and optimizing VLSI layout at the cell and/or block level is required.Additional Desired Qualifications- Good knowledge of VLSI process and device physics- Exposure to physical verification tools, including DRC, LVS, ERC, density, and DFM checks.- Unix and shell scripting exposure- Knowledge of CAD layout tools eg Cadence Virtuoso Synopsys Custom Compiler any other industry-standard layout development tool- Knowledge of scripting languages TCL, Perl, Skill, and Python for design automation is a plus