Cisco Design Verification DV Engineer 

United States, California, San Jose 

250915015

The application window is expected to close on 11/29/2024

You will participate in the ASIC design verification and Emulation for Cisco high-end switching products. One of the largest and most sophisticated of its kind in the industry. Use the microarchitecture and define the verification plan and be responsible for the entire verification process. Develop the verification environment, including creating and executing test plans, and perform any necessary debugging. You will take part in the development of simulation models, test plan, code or functional coverage, multi-chip/system simulation, and performance analysis.

You will work with front-end RTL Design and Verification teams and Architects to understand chip architecture and drive design verification requirements. You’ll work with SDK and Software teams as part of ASIC development to create a flawless handshake between hardware and software functionalities and qualify use-case requirements. You’ll also have the opportunity to work with systems-testing teams during post-silicon validation efforts to bring-up, debug and qualify the ASIC in deployment-mode applications.

We tackle whatever challenges come our way. We have each other’s backs, we recognize our accomplishments, and we grow together. We celebrate and support one another – from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that).