Nvidia Senior ASIC Timing Engineer 

United States, Texas 

250033112

What you will be doing:

• You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, cluster level, and/or full chip level.

• Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets.

• Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.

What we need to see:

• Great teammate

• BS (or equivalent experience) in Electrical or Computer Engineering

• 8+ years experience or MS (or equivalent experience) with 2 years experience in Synthesis and Timing.

• Understanding of DFT logic and hands-on experience in design closure.

• Expertise in analyzing and converging crosstalk delay, noise glitch, andelectrical/manufacturingrules in deep-sub micron processes.

• Knowledge in process variation effect modeling and experience in design convergence taking into account process variations.

• Experience in critical path planning and crafting needed.

• Power user of Static Timing tools like Synopsys PrimeTime or Cadence Tempus.

• Solid experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.

• Proficiency in Python, Tcl and Make for automation and scripting tasks.