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Intel SOC Design Engineer RTL/Logic 
United States, Oregon, Hillsboro 
245721224

Yesterday
Job Description

Your responsibilities may include, but not be limited to:

  • Develops the logic design, Register Transfer Level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.
  • Participates in the definition of architecture and microarchitecture features of the block being designed.
  • Performs Quality checks in various logic design aspects ranging from RTL to timing/power convergence.
  • Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
  • Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
  • Works with IP providers to integrate and validate IPs at the SoC level.
  • Drives quality assurance compliance for smooth IP-SoC handoff.

The ideal candidate should exhibit behavioral traits that indicate:

  • Self-motivator with strong problem-solving skills.
  • Good leadership capabilities.
  • Excellent interpersonal skills, including written, verbal, and presentation communications.
  • Attention to detail and organizational skills.
  • Ability to work as part of a team and collaborate in a high-paced atmosphere.
Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • BS degree in Electrical Engineering, Computer Engineering and 6+ years of experience or MS degree and 4+ years of relevant experience.
  • Relevant experience includes a combination of any of the following:
    • Silicon design, VLSI design, Microarchitecture definition, RTL development, Verification, Post-silicon testing.
    • Client micro-architecture, including power management flows, and memory ordering and coherency.
  • 2+ years of experience in leading functional technical teams.

Preferred Qualifications:

  • 3+ years of experience in front-end design and/or integration.
  • Experience with Python, Perl, or other scripting languages.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits Annual Salary Range for jobs which could be performed in the US $139,710.00-$197,230.00*Salary range dependent on a number of factors including location and experience