Nvidia Senior SOC Design Engineer 

India, Karnataka, Bengaluru 

243322762

What you'll be doing:

• You are encouraged to understand all features of a given project and define project milestones based on internal roadmaps, assign them and track them through agile framework

• Define and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.

• Work on SOC Assembly and drive cross-functional teams towards SOC milestone execution.

• Be responsible for integrating all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification atcluster/sub-system/SOC/emulationlevels.

• Have good grasp of Perl, Python, or other industry-standard scripting languages.

What we need to see:

• BS (or equivalent experience) / MS with 5+ years of practical semiconductor design and architecture experience building complex SoC’s.

• Must have firsthand experience & solid understanding of all phases of SOC development in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical design.

• Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).

• C/C++ programming or python or any other industry-standard scripting language experience desirable.

• Experience working with software teams to tightly define the HW/SW interface including control/status registers, interrupt and error handling.

• Hands on experience in successful tape outs of multiple complex, high-volume SoCs in advanced process nodes.

• Exposure to various Chip Design Functions to be able to collaborate and solve complex cross functional problems.

• Experience in synthesis, physical design and DFT is a plus & Experience in RTL Build and Design Automation is a plus.

Ways to Stand out from the crowd:

• Chip lead type of technical leadership experience on delivering complex SOCs for enterprise and/or HPC applications.

• Experience in RTL coding and debug, as well asperformance/power/areaanalysis and trade-offs

• Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.

• Prior experience of smartNIC and/or high-speed interconnect, strong coding skills in Perl, Python, or other industry-standard scripting languages.

• SOC bring-up and post silicon validation experience