Chip Modeling and Packaging CAD team is responsible for development and support of infrastructure tools for build and verification of architectural, rtl, and gate level designs. Our tools enable our chip design teams to work on state-of-art design technologies such as CoWoS-L. As a software engineer, you will craft highly efficient software to automate and facilitate chip design and verification engineering workflows and processes, and look for ways to advance CAD tools using AI.
What You'll be Doing:- Work as a team to build reliable, scalable and high performance software that are easy to use by hundreds of engineers worldwide.
- Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs).
- Research and develop software solutions to allow greater efficiency in architecture, hardware and software teams.
- Optimize the daily workflows of the world's top chip modelers and designers.
What We Need to See:- BS (or equivalent experience) and 10+ years of software development experience, MS (or PHD) preferred.
- Experienced with C++ or Golang, Unix/Linux.
- Solid understanding of algorithms, computer architecture and computer science theory
- Experienced with VLSI physical design and packaging
- Passionate about SW development processes
- Flexibility/adaptabilityfor working in a dynamic environment with different frameworks and requirements
- Excellent communication, interpersonal and customer collaboration skills
Ways to stand out from the crowd:- Expertise in architecture, RTL design, netlist, placement and routing, power and thermal analysis
- Strong expertise in modern C++, compiler, build systems, and database.
- Experienced with static and dynamic code analysis tools
You will also be eligible for equity and .