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Nvidia Senior Reset Boot ASIC Engineer 
United States, Texas 
232727864

02.07.2025
US, CA, Santa Clara
US, CA, Remote
time type
Full time
posted on
Posted 6 Days Ago
job requisition id

NVIDIA is looking for aSenior Reset and Boot ASIC Engineer


What you’ll be doing:

  • Be an integral part of the System ASIC Design team to help with the Micro-architecture definition for system-level functions, including Reset and Boot.

  • Collaborate with architects, ASIC designers, and verification engineers to design sophisticated system-level modules such as Floorsweep, In-silicon measurement, Reset and Boot controllers.

  • You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules.

  • Integrate modules into the overall SOC design and work closely with other teams in the silicon bring-up process and ensure successful SOC level integration.

  • You will also use your expertise to identify and implement improvements in the current design flow and methodologies to improve efficiency and quality.

What we need to see:

  • BS / MS in Microelectronics/ Electronic Engineering/ Computer Science and related (or equivalent experience)

  • 5+ years of SoC design/integration experience, including architecture and implementation of system-level functions like Reset or Chip Boot

  • Solid frontend ASIC design skills, including RTL design, asynchronous and synchronous Reset design, synthesis, timing analysis, and Spyglass/CDC/RDC checks

  • Excellent analytical and problem-solving skills and attention to detail.

Ways to stand out from the crowd:

  • Broad knowledge with GPU techniques, SOC architecture, Computer architecture, and ARM/RISC-V CPU

  • Experience with general interface protocols such as PCIE, CXL, UCIE, AMBA, and CHI

  • Familiar with OCP secure boot specification and physical security handling process

  • Possess design experience with cross-die/chipset communication in multi-dielet/chipset systems

  • Proficient in Perl/Python scripting

You will also be eligible for equity and .