Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
3 years of experience with Register-Transfer Level (RTL) coding using Verilog/SystemVerilog.
Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
5 years of experience in Application-specific integrated circuit (ASIC) design.
Experience working on interconnects and network subsystems.