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The Role:
Our Interconnect team develops the Arm Corelink Interconnect IP. This highly scalable IP is designed for intelligently connected AMBA-compliant SoC connectivity and can be customized for multiple performance points.
Preferred Experience:
· Micro-architecture experience in PCI Express Transaction Layer and strong familiarity with Data Link Layer and Physical Layer
· Solid understanding of topics including transaction ordering, virtualization, MMUs, cache coherence, and host bridge functions
· History of high quality, low power, high performance complex micro-architecture and RTL implementations in reasonable timescales
· Experience with synthesis, static timing, and DFT
· Experience with physical design methods
· Knowledge of other high-speed interfaces such as AMBA CHI and/or AXI, CXL, Ethernet, DDR
· Experience with scripting languages including Perl, Unix, and Makefiles
· Strong communication, collaboration, and presentation skills
Education Level:
Bachelors or Master’s degree or equivalent experience in Electronics and Communications Engineering/Computer Science Engineering
In return:
We offer a driven reward package including annual bonus, RSUs, healthcare and wellness support. As well as other benefits such as a supplementary pension, and 25 days annual leave (with option to buy an additional 5 days per year).
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