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Apple SoC Physical Design Engineer PnR United States, California, Sunnyvale 218879769
21.04.2025
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In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology.
- Minimum BS and 8+ years of relevant industry experience.
- Ability to adhere to stringent schedule and die size requirements.
- Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ.
- Experience with sub 10nm tech nodes.
- Strong communication skills.
- Experience with partition level P&R implementation including floorplanning, clock and power distribution, timing closure, physical and electrical verification.
- Knowledge of physical design construction and analysis flows and methodology.
- Experience with industry standard tools, understanding their capabilities and underlying algorithms.
- Post silicon debug skills and DFT, ATPG, ATE knowledge.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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