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Google SoC Physical Design Lead Full Chip Implementation India, Karnataka, Bengaluru 203120599
11.04.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 10 years of experience in physical design full chip implementation.
- Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, FC).
- Experience in sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.
Preferred qualifications:
- Master's degree in Electrical Engineering or a related field.
- Experience in floorplanning and block integration.
- Experience in low power design Implementation including Unified Power Format (UPF), multi-voltage domains, and power gating.
- Experience with ASIC design flows and methodology of physical design.
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