Microsoft Principal Engineer Mask Layout 

United States, North Carolina, Raleigh 

202309431

engineers to help achieve that mission.

Semi and Custom IPand industry knowledge to envision and implement future technical solutions that will manage andthe Cloud infrastructure.

Required Qualifications:

• 9+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
• 9+ years of experiencein custom SRAM MemoryLayout.
• 9+ years of experience usingCalibreand Cadencetools

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:

• Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Experience withusing and setting upAnsys Totem.
• Deep knowledge ofcustomdigitallayoutdesign.
• Expertisein Python,SKILL,orTCLscripting and C programming.
• Good communicationskills.
• Excellentproblem-solving skills and creative thinking.
• Proficiencywith 5nm and/or 3nm technology nodes.
• Proventrack recordof delivering high quality memory layout designs.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until November 27, 2024.

• Custom SRAM Layout Implementation : Lead the detailed layout of SRAM cells, memory arrays, and peripheral circuits, focusing on achieving optimal placement, routing, and electrical performance for custom designs.
• Design Rule Checking (DRC), Layout vs. Schematic (LVS), DFM, Antenna, and SRAM Checkers : Ensure all layout designs adhere to the foundry's design rule checks for manufacturability, perform layout vs. schematic checks to verify that the physical layout matches the circuit design, address design-for-manufacturability and antenna effects, and utilize foundry SRAM checkers to ensure compliance with technology node requirements and improve design reliability.
• Optimization : Optimize layout for performance, power, and area, implementing advanced techniques to minimize parasitics and improve overall design efficiency.
• Cross-Functional Collaboration : Work closely with circuit designers and other layout designers, both internal and external to the memory team, to understand design requirements and constraints, translating them into efficient layout designs.
• Tape-out Readiness : Prepare layout for final tape-out, ensuring all necessary checks and validations are completed.
• Technical Leadership and Mentorship : Serve as one of the tech leads with the ability to help drive multiple macros while working closely with the layout manager, providing guidance and mentorship to layout engineers, and fostering a collaborative and innovative environment.
• Stay Updated : Keep up with the latest trends and advancements in layout design tools and methodologies.
• Embody our and