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Google Integration Methodology Flow Physical Design Engineer Silicon United States, California, Mountain View 197227343
26.06.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience with SoC Integration focused on low power design.
- Experience with new process technology based SoC integration flow development and tape-out.
- Experience with scripting languages (i.e., Python, Bash, Tcl) for workflow automation and data visualization.
- Experience with physical design flow development and design closure for multiple ASIC/SoCs.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in System-on-a-Chip (SoC) integration, including 2.5D and 3 Dimensional Integrated Circuit integration and sign-off.
- Experience in extraction of ASIC design parameters, Quality of Results (QoR) metrics, and analyzing trends.
- Experience in co-optimization to enable schedule sensitive development with consideration of block complexity, power domains, clocking, congestion, etc.
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