M.S Degree with 4~7 years relevant work experience
Familiarity with all aspects of Signal Integrity for high speed SerDes, parallel bus, single ended signaling.
Ability to complete channel analysis with Signal integrity EDA.
Measurement expertise with frequency and time domain tools (VNA, TDR) including calibration methods.
Ph.d with minimum 3~5 years experience.
Deep knowledge system level SerDes design and analysis skills. The SerDes knowledge required includes understanding of transmitter and receiver equalization methods (including FFE, CTLE, DFE, VGA gain), CDR behaviors and modeling, link training algorithms and eye margining tool.
Serial bus expertise shall include knowledge of the specifications of PCIe, USB, DisplayPort, HDMI and Thunderbolt. SI skills required include DOE analysis across channel variants, applying equalization and training as required for end-end channel analysis.
Excellent documentation and communication skills, ability to work independently, a desire to mentor, and demonstrated ability to innovate are required
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.