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Intel CPU Design Engineering Manager United States, California, San Jose 185113390
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The successful incumbent in this position will perform the following but not limited to:
Leads and manages CPU silicon design teams within one or more areas of functional development including logic design, verification, circuit design, and/or physical design for a CPU.
Manages the engineering team resources, their functions, activities, responsibilities, and driving continuous improvement and silicon quality standards.
Takes active part in defining CPU microarchitectural features and drives their implementation.
Conducts design reviews to ensure key factors such as power, performance, area, and cost are meeting requirements.
Works to continuously to improve CPU silicon development processes and architecture definition across areas of CPU silicon design.
Oversees and reviews design verification test results, data analysis, issue tracking, root cause analysis, and drives corrective actions implementation for silicon design.
Works closely across other IP and SoC development teams that integrate the CPU to design complex projects, ensure quality, drive performance, and design implementation.
Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. Drives results by inspiring people, role modeling Intel® values, developing the capabilities of others, and ensuring a productive work environment.
Provide daily technical guidance to the team to implement designs in RTL and execute design flow to tape out designs to meet schedules.
Resolve conflicts
Manage the design team in cross functional meetings, prepare team status, manage hiring
Education Requirements
B.SC. electrical engineering or related field.
Minimum Qualifications
10+ years of experience in the following:
CPU architecture and design for ARM and CPUsubsystemsincluding cache architecture and coherency.
Programming model of peripheral IPs such as USB, Ethernet, I3C, PCIe.
Coherent and non-coherent Network-on-Chip architecture and design
CPU subsystems integration challenges and tradeoffs for power, performance and area
Preferred Qualifications
Master’s Degree with 6+ year or PHD with 4+ years in electrical engineering or related field
6+ years of experience in any of the following:
ASIC flow from RTL to GDSII with
Synthesis, place and route, physical implementation,
Constraint design, timing closure,
DRC/LVS, DFT, DFD, memory designs, clock
Reset circuits, low power modes, packaging tradeoffs
*Salary range dependent on a number of factors including location and experience
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