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Job Area:
Engineering Group, Engineering Group > ASICS Engineering
Job Description:
Principal Duties and responsibilities
Develop constraints for physical power aware synthesis, low power multi voltage domain checks, static timing analysis and power aware formal verification.
Work closely with RTL design, physical design teams to optimize area, performance and power.
Generate, review and validate clock domain crossing, design constraints to achieve timing closure of complex soc cores.
Tabulate metrics results for QOR comparison. Analyze trade off in area power and performance.
Manual and conformal EcOs for post netlist modifications.
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
Pay range:
$158,000.00 - $237,000.00
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