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Google ASIC Design Verification Engineer Machine Learning
United States, California, Sunnyvale
178261909

11.04.2024

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Minimum qualifications:

Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
Experience with SystemVerilog (e.g. SystemVerilog Assertions or functional coverage).

Preferred qualifications:

Master's degree or PhD in Electrical Engineering.
Experience with Universal Verification Methodology (UVM).
Experienced with the full verification life cycle.

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