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Apple Digital-Mixed-Signal Verification Engineer m/f/d Germany, Bavaria, Munich 17634200
06.06.2024
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Description
In this position you will be developing analog behavioral models in System Verilog, running model versus schematic correlation simulations to guarantee the matching to the schematic specifications, defining/verifying verification requirements, coding of test scenarios and assertions, doing sub-/system verification with existing UVM top-level test benches, interacting with analog and digital design engineers, firmware engineers, RF layout engineers.
Key Qualifications
- Experience in analog design is a must
- Experience with digital simulation tools like Cadence NCsim, Synopsis VCS, Mentor Modelsim, and/or Mixed Signal simulation tools (such as Cadence AMS-Designer, Synopsis VCSXA, Mentor Questa).
- Ability to read and understand schematics to define and implement functional behavioral models
- Ability to think on different abstraction levels from very detailed components to system-level
- 3+ years of experience in hardware description languages like System Verilog, VHDL, and Verilog is desired
- Outstanding sense and drive for the quality of work you're doing
- Verification mindset and approach
- Reliable, ability to work independently as well as in a team environment
- Good interpersonal and communication skills
- C/C++ programming language for test case development is a plus
- Proficient English skills are a requirement
- System know-how in the cellular RF transceiver domain is an advantage
Education & Experience
Bachelor’s or Master's degree in Electrical Engineering or Computer Engineering, Mechatronics, Electronics, or equivalent.
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