Amazon Hardware Development Engineer AWS Center Quantum Computing 

United States, California, Pasadena 

174550629

Key job responsibilities
Responsibilities include developing, improving, and sustaining fabrication and packaging process flows; collecting and analyzing inline metrology and electrical test data; writing and maintaining production standard operating procedures; interacting with project leads to provide feedback that continuously improves the process. Candidates must have a demonstrated background in sound engineering principles, and must have good data analysis, problem solving, and communication skills and be highly motivated and curious to research and learn new technical topics as needed. Working effectively within a team environment is critical.A day in the lifePasadena, CA, USA

- Bachelor’s degree in electrical engineering, material science, mechanical engineering, or other relevant technical fields, or equivalent practical industry experience
- 5+ years of relevant industry experience working in a cleanroom environment (3+ years with a Master’s degree and 1+ years with a Ph.D. degree in a relevant field)
- Hands-on experience in photolithography (mask or maskless aligners, steppers, and scanners); wafer-level wet/dry etching techniques; wafer cleaning and lift-off techniques; thin film deposition techniques (e.g., PECVD, LPCVD, ALD, evaporation, sputtering, and furnace oxidation); semiconductor and thin film metrology techniques (e.g., SEM, profilometry, reflectometry, and ellipsometry); one or more manufacturing execution systems
- Strong verbal, written, and data presentation skills
- Effective at managing multiple tasks/projects and working independently or within a team environment with other engineers, scientists, and technicians who might have a wide range of technical skill levels

- Experience in fabricating superconducting quantum circuit and/or packaging components
- Great problem solving and analytical skills
- Hands-on experience with electron beam lithography; electroplating; wafer thinning; chemical mechanical polishing; wafer level and flip-chip packaging techniques; temporary and permanent wafer level bonding; 2.5/3D integration schemes
- Experience in performing failure analysis and root cause investigation for process excursions
- Working knowledge of statistical analysis and design of experiments using JMP or minitab
- Experience in yield monitoring, statical process control, and demonstrating process capability