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You'll work on the design and development of our next generation custom SRAM design. As part of the Digital IP Team, you will work with other team members on the new process design challenges. You will have the chance to work on custom and compiler ram layouts with cut in edge process technology that would be used on all the NVIDIA products!
What you'll be doing:
Perform physical layout for custom embedded SRAM structures in state-of-the-art sub-micron CMOS technologies using Cadence tools.
Assist in taking part in floor planning, custom layout and verifying against design rules and schematics.
Perform power robustness check and EMIR verification and fixes
Negotiation with P&R on setting up ram interface spec
Lead and influence other layout designers to improve team efficiency and align design methodology
What we need to see:
Associates degree (or equivalent experience).
8+ years proven experience in mask and layout design.
Deep understanding of digital and analog circuit layout concepts in submicron CMOS technologies.
Strong background with Cadence custom circuit design tools - particularly Virtuoso.
Experience running and debugging with verification tools such as ICV or Calibre
Knowledge of DRC and LVS checking flows, ability to customize decks
Strong communication skills
Prior management experience preferred
Can effectively work in a team, good interpersonal skills, passion and positive energy.
Ways to Stand Out from the Crowd:
SRAM digital custom block design experience
SRAM compiler experience
You will also be eligible for equity and .
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