Microsoft Senior Design Verification Engineer 

United States, California, Mountain View 

166165884

Required Qualifications:

• 7+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 6+ years of experience in design verification with a proven track record of delivering complex Central Processing Unit(CPU) or SoC IP’s.
• Knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments.
• Background in debugging Register Transfer Level(RTL) Verilog designs as well as simulation and/or emulation environments.
• Experience in Scripting language such as Python or Perl.

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Good understanding of computer architecture.
• Hands on experience in Formal property verification.
• Processor based testbenches and emulation.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until July 20, 2024.

The AISiE silicon team is seeking a
Senior Design Verification Engineerto deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom Internet protocol(IP) and System on Chip(SoC) designs that can perform complex and high-performance functions in an extremely efficient manner.

• Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology(UVM), or formally verify designs with SystemVerilog Assertions(SVA) and industry leading formal tools.
• Develop tests using UVM or C/C++.
• Analyse and debug test failures with designers to deliver functionally correct design.
• Identify and write functional coverage for stimulus and corner cases.
• Close coverage to plug verification holes and meet tape out requirements.
• Other
  • Embody our and