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Google Technical Lead ASIC IP Subsystem Design Silicon India, Karnataka, Bengaluru 159952148
26.06.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience in ASIC design.
- Experience in RTL development with Verilog/SystemVerilog.
Preferred qualifications:
- Master's degree or PhD degree in Materials Science, Electrical Engineering, Computer Engineering, Physics, or a related field.
- Experience in High performance design, Multi power domains with complex clocking and multiple SoCs with silicon success.
- Understanding of computer architecture including industry standard interfaces and memory subsystems.
- Proficient with micro architecture design and good knowledge of system design to develop highly optimized IPs with excellent PPA.
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