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What you’ll be doing:
Integrations and Full-Chip models
Verification for chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area, and performance
Daily work involves all aspects of Design Verification : Planning, Coding, Coverage and Integration.
What we need to see:
B.SC./ M.SC. inComputer Engineering/Electrical Engineering/Communication Engineeringor equivalent experience
5+ years of overall hands-on experience
Validated experience in Verification or RTL Front-end ASIC Design
High Level of English
Ability to work as part of a team
Ways to stand out from the crowd:
Background in Specman or UVM
Knowledge in HDL (Verilog/VHDL)
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