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Google Senior SOC RTL Design Engineer Google Cloud Israel, Tel Aviv District, Tel Aviv-Yafo 154116991
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Note: By applying to this position you will have an opportunity to share your preferred working location from the following:.
- Bachelor's degree in Electrical Engineering, Computer Science, a related technical field, or equivalent practical experience.
- 8 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
- Experience in logic design and debug with Design Verification (DV).
- Experience with PCIe (PCI).
Preferred qualifications:
- Experience in scripting languages like Python or Perl.
- Knowledge of high performance and low power design techniques.
- Knowledge of System-on-a-Chip (SoC) architecture.
- Domain knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors.
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