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Google Formal Verification Engineer Platform IP India, Karnataka, Bengaluru 153555599
Yesterday
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 3 years of experience with SystemVerilog and SystemVerilog Assertions.
- Experience with formal verification.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Science, or a related field.
- Experience with scripting languages, such as Python/Perl and TCL.
- Experience with formal sign-offs of industry ASIC designs.
- Knowledge of formal verification applications such as sequential equivalence checking, and connectivity checking and data-path verification.
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