Cisco Principal Software Engineer MX Networking 

United States, Georgia, Atlanta 

151363097

As a Principal Engineer on the MX team, you will be in charge of designing, developing, and implementing the architecture of various MX technologies such as SD-WAN, cellular, security, containers, routing, etc. The team will look up to you as a primary architect. This role needs a very experienced, hands-on, and hardworking engineer who can improve the current architecture, plan for next-generation architecture, and partner with Product Management and MX leads to define the next generation technical roadmap on merchant as well as custom silicon.

Apart from data plane architecture, this role will also serve as the main architect in new product development, new technologies implementation for overall MX

• Be at the forefront of architecture, design, and implementation of MX new generation of high-performance appliances and platforms
• Develop packet processing and routing capabilities across MX
• Participate and lead various architectural discussions
• Define the next generation product
• Guide the team of hardworking individual contributors to craft the architecture

• 12+ years of working experience on data plane forwarding and control-plane configuration, signaling for embedded routing, and SD-WAN products.
• Deep knowledge of routing protocols and SD-WAN
• Hands-on experience and crafting on more than one data plane technology across arm and x86. DPDK, NETMAP, VPP, CLICK
• Understanding and experience of L4 to L7 services (like load balancing flows, firewall, IPSec VPN, NAT, IPv6, remote access and various tunneling protocols), architectures, and algorithms
• Experience writing Linux user and kernel code for high-performance fabrics, I/O devices
• Successful delivery on multiple high-performance products
• Ability to work independently as well as in a team
• Good communication skills and experience working with cross-functional teams

• Good understanding of VPP or CLICK data plane
• Merchant silicon SDKs from Broadcom, Marvell, EZchip, etc.
• Layer 2 / Layer 3 functionality, application-aware packet processing