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What You'll Be Doing:
Use Emulation platforms like Zebu and Palladiums to emulate benchmark traces.
Develop testbench capabilities to fast track and automate emulation waveform captures.
Use internally developed tools and industry standard pre-silicon Gate-level and RTL power analysis tools, to help report power.
Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.
Interact with Architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.
Select and run a wide variety of workloads for power analysis.
Prototype a new architectural feature in Verilog and analyze power.
What We Need To See:
BS or MS (or equivalent experience) with 5+ years of experience or PhD in related fields.
Strong analytical skills, attention to detail, systematic approach to debug and curiosity to learn.
Strong coding/automation skills, preferably in Python, and/or C++.
Background in emulation with intent to perform hand on debug on daily basis.
Good understanding of concepts of energy consumption, estimation, data movement and low power design.
Familiarity with Verilog and ASIC design principles, including knowledge of Power Artist, PTPX (Prime Power RTL, RTL Architect).
Good verbal/written English and interpersonal skills; much collaboration with design teams is expected.
Desire to bring data-driven decision-making and analytics to improve our products.
You will also be eligible for equity and .
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