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What you'll be doing:
Develop and deploy Industry-leading test methodologies on NVIDIA’s next-generation silicon platforms.
Collaborate with leading EDA vendors to shape tool capabilities that meet NVIDIA’s ambitious design goals, and partner with internal CAD teams to drive scalable, automated solutions.
Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to push the boundaries of silicon test innovation.
Own the full ATPGlifecycle—verification,
Guide and mentor junior engineers, helping them navigate complex design trade-offs to achieve world-class quality and efficiency.
What we need to see:
MS/PhD or equivalent experience in Electrical Engineering or a related field
5+ years of hands-on experience in Design-For-Test (DFT)
Deep knowledge of DFT tools, methodologies, and test strategies for complex, large-scale designs
Clear, effective communicator—strong written and verbal skills
Passion for mentoring and scaling technical excellence in a team
Ways to stand out from the crowd:
Experience with 2.5D/3D ICs, multi-chiplet architectures, or reticle-sized designs
Background in developing or enhancing EDA tool flows
Experience with Silicon testing and Automatic Test Equipment (ATE)
Expertise in using programming languages and AI for automation
Personal success stories in leading org wide changes
You will also be eligible for equity and .
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