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What you’ll be doing:
As a senior member of our verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), come up with and implement test/coverage plans, and verify the correctness of the design.
Collaborate with NVIDIA memory controller designers and DRAM vendors to bringup/debug challenging issues related to the next generation of LPDDR and DDR memories
Ensure code and functional coverage of all the RTL which you will verify.
Work with and enable FPGA and software teams to ensure that software is tested.
Be involved with post-silicon verification and debug.
What we need to see:
BS / MS or equivalent experience.
4+ years of hands-on ASIC verification of challenging design units over multiple projects displaying good attention to detail, teamwork, problem solving and proven success
Prior Design or Verification experience of dynamic memory controllers (ddr{2, 3, 4, 5}, lpddr{2, 3,4,5, 6})
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
Background with System Verilog and UVM based methodology for ASIC verification.
Ways to stand out from the crowd:
Strong C/C++ programming experience
Proficiency in debugging and resolving issues
Scripting knowledge (Python/Perl/shell).
Good interpersonal skills and ability & desire to work as a part of a team.
You will also be eligible for equity and .
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