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Apple ASIC Design Engineer United States, West Virginia 144238206
05.09.2025
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- Master’s degree or foreign equivalent in Electrical, Electronics or Computer Engineering, Computer Science or related field.
- Experience and/or education must include:
- Utilizing programming language (Python, Perl, or TCL) for building front-end flows used in RTL generation, RTL verification, RTL analysis and design integration
- Utilizing RTL, Gate, and DFT Linting tools and techniques, and knowledge of System Verilog standards to design SoC along with building and maintaining Front-End flow using Perl and Python
- Debugging software and RTL using an interactive debugger, including IntelliJ, VSCode, Gvim or Emacs, to triage and root cause issues
- Experience operating in Linux OS, database technologies, revision control systems and virtual environments
- Experience with ASIC clock methodology and tracing logic fan-in and fan-out of RTL and gate-level designs
- Experience using regular expressions for writing scripts that can parse or process data from log files generated by Front-End flows
- Experience with Front-End design concepts and tools including Static Timing Analysis or Primetime or Xcelium or VC Static
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