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What you will be doing:
We support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches).
Bring up SOCs on emulation, root causing SoC/Processor test fails and emulator environment issues.
We have continual collaboration with Design, DV, Power, Silicon Validation, Performance, and Software teams.
Work constructively leading emulation vendors to debug issues using various tools.
What we need to see:
M.S or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering or related field.
3+ years of proven experience.
Individual should be proficient in Verilog and/or VHDL, C/C++ and SystemVerilog.
Experience with UVM verification environments and scripting with Perl, Python and C/C++ is essential.
Be familiar with hierarchical design approach, top-down design, SoC and system level verification.
You will also be eligible for equity and .
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