Nvidia Analog Digital Mask Design Engineer 

India, Karnataka, Bengaluru 

127492953

What you'll be doing:

• Execute IC layout of cutting edge, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 2nm, 3nm, 5nm, 7nm and lower nodes following industry best practices.

• Deliver layouts for Circuit Solutions Group specializing in digital cum analog IPs.

• IP layout will comprise of significant digital components and some analog components.

• Adopting and putting in place best layoutpractices/methodologyfor composing Analog and digital layouts

• Follow company procedures and practices for IC layout activities.

• Perform full custom layout of analog/mixed-signal blocks such as op-amps, bandgaps, PLLs, ADCs, DACs, LDOs, Voltage Regulators etc.

• Ensure design quality by adhering to matching, symmetry, and parasitic sensitivity requirements.

• Execute layout verification (DRC, LVS, ERC, Antenna checks, EMIR) and resolve violations.

• Optimize layouts for area, performance, and manufacturability.

What we need to see:

• 4+ years of experience in high performance analog layout in advanced CMOS process.

• BE/M-Tech in Electrical & Electronics or equivalent experience.

• Thorough knowledge of industry standard EDA tools for Cadence.

• Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps etc. is required.

• Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines)

• Experience with floor planning, block level routing and macro level assembly.

• Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines.

• Demonstrated experience with analog layout for silicon chips in mass production.

• Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred.

• Experience working in distributed design team is a plus.

• Requires self-starter with the ability to define and adhere to a schedule.