Microsoft Senior Design Verification Engineer 

United States, California, Mountain View 

126950330

Required/Minimum Qualifications:

7+ years of related technical engineering experience

• • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 7+ years of experience in design verification with full verification cycle on complex System On Chip (SOC) IPs and/or systems.
• 5+ years experience with verification principles, testplan development, testbench creation, stimulus generation, Universal Verification Methodology (UVM) and coverage, debugging designs as well as creating simulation environments, with a proven track record of full verification cycle on complex SoC IPs and/or systems.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check:

• • • This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred/Additional Qualifications:

• Knowledge of verification principles, testbenches, stimulus generation, UVM, and coverage.
• Experience in creating simulation environments, developing tests, and debugging designs.
• Understanding of chip and/or computer architecture.
• Experience wiith scripting language such as Python, Ruby.
• Experience with System Verilog and UVM
• Hardware security IP and SOC level verification
• Firmware development experience, with secure and non-secure boot flow

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until June 28, 2024.

• Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom Intellectual Property (IP) components.
• Define pre-Silicon verification (simulation/emulation/formal proofs/field-programmable gate array (FPGA) and post-Silicon validation strategies.
• Work with a team to write, execute, enhance, and debug constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness.
• Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments.
• Define and implement functional coverage and drive coverage closure.
• Collaborate across verification teams on vertical and horizontal reuse of components.
• Interact with Architecture, Design, Firmware/Software, Product Engineering, Program Management and third party vendor teams to ensure pre-and-post-Silicon testing is comprehensive.
• Write scripts for verification and validation infrastructure.
• Apply Agile development methodologies including code reviews, sprint planning, and feature deployment.
• Provide technical leadership through mentorship and teamwork.

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