Broadcom Verification Engineer 

United States, California, San Jose 

122563356

Job duties include:

• Verify a block/Core/SOC and complete assigned tasks to closure.

• Write scalable and re-usable testbenches from scratch, using the framework of the verification methodology like UVM

• Develop Testplans, participate in reviews, write Functional Coverage

• Develop Psuedo-random Test cases, Verify the feature and close Functional Coverage and stabilize regressions

• Look for opportunities to improve quality and efficiency.

• Participate in documentation of verification strategy including test plans, verification micro-architecture, coverage objects etc.

Requirements:

• Bachelor's degree in Electrical Engineering or related degree with 8+ years Verification experience or Master's degree in Electrical Engineering or related degree with 6+ years of Verification experience

• Must have worked on complex Verification tasks.

• Must have good working knowledge in constrained random verification and very good understanding methodologies like UVM/VMM/OVM

• Must be proficient with System Verilog

Compensation and Benefits

The annual base salary range for this position is $119,000 - $190,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.