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QT Technologies Ireland Limited
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
Responsibilities will include:
Work with Architecture, Design team to understand the low power design features and create verification plan
Develop test plan document for the design features and get them reviewed with design team
Develop verification components, testbench for low power verification and integrate third party VIPs/UVCs as required
Create constraint random verification environment using System Verilog, UVM
Follow company defined verification methodologies
Perform Power Aware Verification in a random verification environment with embedded firmware running on the design
Regress and close the required Low Power coverage metrics to ensure high quality design
Create portable test setup, verification components that can be reused across simulation, emulation platforms
Perform failure debug involving hardware software co-debug
Work with tool vendors and push the methodology to improve the verification flows.
System level RTL simulation & design verification.
Support SoC DV for their integration verification, chip bring up and post silicon debug.
Minimum Skills:
Bachelor’s degree in Science, Engineering, or closely related field
3+ years of hands on experience in System Verilog, OVM/UVM based constrained random verification.
3+ years in Design validation/Post-Silicon debug.
3+ years of hands on experience in developing verification components/UVCs, testbench for RTL verification
3+ years of hands on testbench bringup, integrating third party VIPs, digital design, verification, debugging, and waveform debug
2+ years of experience in UPF based Power Aware verification
2+ years of experience in Functional coverage model development and/or code coverage closure
Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells.
Desirable:
MS degree in Electrical Engineering or equivalent; 8 years of practical experience
Experience with Synopsys NLP (native Low Power) tool.
Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus
Power Aware Emulation verification experience
Hardware/Software Co-verification
Worked on Low Power coverage metrics collection and coverage closure
Knowledge of GPU/CPU/DDR/Bus preferred
Scripting skills using Python
Formal verification experience (AND/OR) Low Power Formal Verification experience
Where you will be working
A gateway to Europe, Cork airport provides access to almost 50 international destinations including transatlantic air routes.
What's on Offer
Apart from working in an open, relaxed and collaborative space, you will enjoy:
Salary, stock and performance related bonus
Maternity/Paternity Leave
Employee stock purchase scheme
Matching pension scheme
Education Assistance
Relocation and immigration support (if needed)
Life, Medical, Income and Travel Insurance
Subsidised memberships for physical and mental well-being
Bicycle purchase scheme
Employee run clubs, including, running, football, chess, badminton + many more
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
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