Nvidia Senior ASIC Physical Design PPA Engineer 

United States, Texas 

118735908

What you'll be doing:

• Drive physical design and timing of high-frequency and low-power designs

• Focus on improving the PPA (Performance, Power, Area) for the next generation NVIDIA designs by working with cross-functional teams

• You will focus on generating new ideas, validating those, putting together flows/methodologies around those, and incorporating those in NVIDIA’s designs

• Apply knowledge and gain experience in ASIC design including RTL and logic design, physical and circuits design, and timing and power convergence
  

What we need to see:

• BS (or equivalent experience) in Electrical or Computer Engineering with 8+ years experience or MS (or equivalent experience) with 6+ years experience in Physical Design

• Expertise in physical synthesis and deep understanding of RTL/logic and equivalence checking to achieve better QOR (quality of results)

• Good understanding of Place-and-Route design as well as associated tools/flows, ability to analyze physical DBs (databases) and drive new ideas

• Hands-on experience in STA and timing closure including multi-mode analysis, timing constraints generation and management, and timing convergence

• Expertise in identifying timing bottlenecks (in design and process) and craft solutions to address those

• Explore and implement low power design ideas by finding the right balance with timing and area

• Good understanding of process and technology nodes, process variations and signal integrity related issues and modeling, and make design recommendations to address those

• Familiarity with logic synthesis, equivalence checking, DFT, Floorplanning, Place & Route, and ECO implementation methodology and industry-standard EDA tools

• Proficiency in programming and scripting languages, such as, Perl, Tcl, Python, etc. and ability to understand and improve existing flows and methodologies

• Strong interpersonal and communication skills to work across different domains of ASIC design, collaborate and work with Arch, RTL, DFT, and physical design teams

Ways to stand out from the crowd:

• Background in high-performance and low-power designs

• Understanding of Device physics, Knowledge of circuits, SPICE simulations, and/or transistor level STA.

• Ability to develop new methodologies/flows as well as workflows to aid design convergence.