Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field and 2 years of experience in the job offered or related occupation.
Experience and/or education with each of the following:
Experience in Computer Architecture, including Cache Coherency, Cache Hierarchy Fundamentals, Fabric Interconnect fundamentals to help debug performance bottlenecks
Experience in Data Structures and Algorithms, including using python, C++ and System Verilog to work on multi-language codebases.
Experience in Object Oriented Programming, including using python, C++ and System Verilog to work on multi-language codebases.
Using waveform viewers to debug performance bottlenecks in hardware, including developing System Verilog monitors to automate performance stat collection
Using C and C++, including updating and reviewing software model used to represent the hardware
Scripting in Python and Perl experience, including using scripting in Python and Perl to analyze and provide visual representation of performance data.
Experience in design verification to help develop robust test plans.