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What you will be doing:
Join accelerators IP group in Beer-Sheva/Tel-Aviv , working on RiscV platform unit
design for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance
Daily work might involve any or all aspects of chip development: Design, micro-arch.
Work closely with Firmware and other groups around the globe
What we need to see:
University B.SC. in ElectricalEngineering/CommunicationEngineering/Computer Engineering or equivalent experience.
2+ years experience in RTL design
High Level of English
Ways to stand out from the crowd:
Experienced in RTL design usingVHDL/Verilog/SystemVerilog
Experienced in CHI protocol or other cache coherence protocols
4+ years experience in RTL design
GPA of 85 and above
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